Investigation of anomalies in an industrial copper electrochemical deposition process

Date

2002-05

Journal Title

Journal ISSN

Volume Title

Publisher

Texas Tech University

Abstract

The demand for faster processors has driven companies to reduce the size of the integrated circuits and to convert the interconnect metal from aluminum to copper. With the advent of copper as the interconnect metal, the metal deposition process has been altered to accommodate new deposition processes onto silicon wafers.

In this research, the characterization of copper thin films that has been associated with the copper deposition process is investigated. This characterization includes the recrystallization and self annealing properties associated with copper, the effects of storage conditions between physical vapor deposition and electrochemical deposition and the historical mass gain that can be monitored by surface acoustical wave analysis.

Crystalline orientation and the topography of deposited copper were monitored. The observations of the Crystalline orientation showed that the copper has a face-centered- cubic structure. Measurements from the topography indicated that the surface roughness of the deposited copper increased with increased time between deposition processes. The effects of the crystalline orientation and the roughness of the surface of the wafer are determined to have an insignificant role in the number of defects observed on pilot wafers.

Light point defect detection equipment was used to allow a non-destructive metrology method that can monitor the number of defects contributed to various storage and loading conditions. The observations made in comparing light point defects with different loading and storage conditions and the observations with the modified Surface Acoustic Wave (SAW) data revealed that the air flow of the clean room has a role in the number of defects witnessed by pilot wafers.

A cover was manufactured to obstruct the air flow over a batch of wafers. The cover reduced the number of light point defects observed on the wafers. The same cover was placed over a SAW device. The resulting data from the SAW device indicated that the cover reduced the mass gain for approximately 6 hours. A full load station cover was built and tested for the ECD tool. The full cover reduced the amount of defects per unit area for production wafers.

Description

Keywords

Copper plating, Electrochemistry, Interconnects (Integrated circuit technology)

Citation