Testing L2 cache in a microprocessor by implementing memory test options

Date

2003-05

Journal Title

Journal ISSN

Volume Title

Publisher

Texas Tech University

Abstract

The intent of this thesis work is to optimize the procedure of testing microprocessor memory. The following work explains a way to optimize memory testing by implementing the Memory Test Option, in other words, by having the memory test patterns generated algorithmically, thereby, achieving a vast amount of pattern size reduction. The Memory Test Option enabled a compression ratio in the order of tens of thousands and freeing the precious resource of tester memory of other purposes.

Description

Keywords

Computer input-output equipment, Computers

Citation