Die level sorting of an integrated circuit

Abstract

The semiconductor industry is one that relies heavily on the reliability of its products. However, the cost of developing reliable products can be considerably high. Expensive testing processes have inspired the companies to develop test reduction methods. One such method is die level sorting. Die level sorting uses wafer level testing to determine if a device will be a reliable product. This paper describes the approach to developing a die level sorting algorithm and then applies the method to develop an algorithm for a semiconductor integrated circuit.