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dc.creatorBlack, Kelley Ann
dc.date.available2011-02-18T21:20:07Z
dc.date.issued2000-12
dc.identifier.urihttp://hdl.handle.net/2346/15966en_US
dc.description.abstractThe semiconductor industry is one that relies heavily on the reliability of its products. However, the cost of developing reliable products can be considerably high. Expensive testing processes have inspired the companies to develop test reduction methods. One such method is die level sorting. Die level sorting uses wafer level testing to determine if a device will be a reliable product. This paper describes the approach to developing a die level sorting algorithm and then applies the method to develop an algorithm for a semiconductor integrated circuit.
dc.format.mimetypeapplication/pdf
dc.language.isoeng
dc.publisherTexas Tech Universityen_US
dc.subjectSemiconductorsen_US
dc.subjectIntegrated circuitsen_US
dc.titleDie level sorting of an integrated circuit
dc.typeThesis
thesis.degree.nameM.S.E.E.
thesis.degree.levelMasters
thesis.degree.grantorTexas Tech University
thesis.degree.departmentElectrical Engineering
dc.rights.availabilityUnrestricted.


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