Design of multiplier and its VLSI implementation

Date

1999-05

Authors

Journal Title

Journal ISSN

Volume Title

Publisher

Texas Tech University

Abstract

A 3-bit recoding algorithm is used to implement a parallel multiplier in two's complement. The circuits at gate level for implementing 8 x 8-bit multiplier are presented. To obtain highest speed, (1) carry skip adders combined with carry select adders are adopted to implement two's complement multiplier, (2) carry save adders combined with carry select adders are used to add partial products. An 8x8-bit multiplier was implemented physically with 1.2^m CMOS SCN (Scaleable N-well) technology using Tanner L-Edit CMOS layout tool. The area of the chip (not including pads frame) is 1 mm . The chip has been fabricated and tested. From the chip test, the execution time is less than 5.7ns. A 16x16-bit multiplier implemented with 8x8-bit multiplier cells using Pspice software tool was also presented. The execution time of the 16x16-bit multiplier is about 1.5 times that of the 8x 8-bit multiplier from the Pspice simulation.

Description

Keywords

Multipliers, Integrated circuits

Citation