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dc.creatorElahi, Noor-E
dc.date.available2011-02-19T00:44:37Z
dc.date.issued2001-08
dc.identifier.urihttp://hdl.handle.net/2346/22072en_US
dc.description.abstractWith the advent of digital networks and the transmission and reception of binary pulses (Is and Os), it became important to devise some method for detecting these signals accurately at the receiver. The ideal system is one in which the binary pulses arrive at the receiver in a very precise and concise manner. This means that the receiver knows the exact time when the signal (a binary 1 or 0) manifests itself at the receiver interface. Fortunately, it is relatively easy to determine this timing, because the receiver can derive the clock from the incoming bit stream by examining when the pulses arrive at the receiver. This function is called cock recovery. The rest ofthe data can be detected using this clock. However, errors can occur if the clock is not aligned with the signal or data. This leads to wrong information in the receiver about the timing of received data. This problem is usually called phase variation, and may translate into an incorrect interpretation of the binary Is and Os in the transmission stream. So it is vital for digital transmission that the data transmitted should be aligned to a pure clock, which has no phase variations. As shown in Figure 1.1, the signal and the clock are perfectly aligned to a clock with no phase variations. The positive edge ofthe clock is at the middle of each 1 or 0. This clock is referred to as a reference clock.
dc.format.mimetypeapplication/pdf
dc.language.isoeng
dc.publisherTexas Tech Universityen_US
dc.subjectSynchronizationen_US
dc.subjectTiming circuitsen_US
dc.subjectDigital communicationsen_US
dc.titleDesign of a clock synchronization circuit
dc.typeThesis
thesis.degree.nameM.S.
thesis.degree.levelMasters
thesis.degree.grantorTexas Tech University
thesis.degree.departmentElectrical Engineering
dc.rights.availabilityUnrestricted.


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