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dc.creatorGarcia-Sagredo, Michelle M.
dc.date.available2012-07-05T18:26:28Z
dc.date.issued2012-05
dc.identifier.urihttp://hdl.handle.net/2346/45380
dc.description.abstractThe work behind this thesis exemplifies a methodology regularly followed in the semiconductor industry in order to identify a root cause to a low yield issue, determine actions to eradicate or ameliorate the problem, design the experiments meant to gather evidence from test wafer lots in support of the suggested improvement, as well as analyzing the experiment’s results and implementing the solution in production wafer lots. Yield Enhancement engineers deal daily with this kind of scenario. It is in their hands to ensure the company’s profitability not only by identifying and fixing the obvious manufacturing recurring problems, but by pointing out areas of opportunity for better process control, and therefore being able to provide higher yield for their customers. The particular issue covered on this paper is the fluctuation of process control parameters from Standard Low Voltage (SLV) P-channel Metal-Oxide-Semiconductor Field Effect Transistors at a certain semiconductor Fab. Historically, the devices processed with the SLV option at this fab have shown severe Threshold Voltage (Vt) variation lot to lot. This variation has lead to whole lots being out of spec, and therefore, scrapped. Due to the high amount of lots processed with this option that have gotten scrapped, finding the root cause for this issue and fixing it became one of the most important goals for the Fab’s Yield Enhancement Engineers in the past years. In order to find a starting point for the solution of the problem, several trends for the parameters of interest were analyzed. The trends indicated a possible correlation of the scrapped lots to the Anti-Punch-Through (APT) Implanter used for their processing. Given the close relationship between the APT and the Threshold Adjust (PVt) Implant, the last one also became an important line of investigation. The theoretical background on CMOS fabrication, the importance of metrics such as Cp and Cpk in the industry, and the approach followed to solve the Fab’s SLV Threshold Voltage fluctuation issue are a few of the topics one can read about on the present work.
dc.format.mimetypeapplication/pdf
dc.language.isoeng
dc.subjectSemiconductor industry
dc.subjectSemiconductors
dc.subjectElectrical engineering
dc.subjectMicroelectronics
dc.titleYield enhancement in microelectronic technologies: Reduction of variability in transistor threshold voltage
dc.typeThesis
thesis.degree.nameMaster of Science
thesis.degree.levelMasters
thesis.degree.disciplineElectrical Engineering
thesis.degree.grantorTexas Tech University
thesis.degree.departmentElectrical and Computer Engineering
dc.contributor.committeeMemberBorhani, Marcus
dc.contributor.committeeChairGale, Richard O.
dc.degree.departmentElectrical and Computer Engineering
dc.rights.availabilityRestricted from online display. For access, please contact the author.


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