Design of charge pump phase locked loop

Date

2012-08

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Abstract

Phase Locked Loop system is around since 1932. The versatility of PLL systems and where it can apply makes it very useful. It can be applied to automobiles as well as cellular chips. This thesis work presents design and analysis of a Phase Locked Loop in IC level. It is implemented and designed in a 0.5um CMOS process. All the blocks of the Phase Locked Loop was designed independently and then integrated together. Phase Frequency Detector, Charge Pump, Low Pass Filter, VCO, Frequency Divider and Level Shifter topologies and circuits are described in detail along with some major design tradeoffs and critical issues.

The uses and implementation of two kind of frequency divider is demonstrated. Their design tradeoffs are utilized to make design effective and robust

Description

Keywords

Phase locked loop, Pump frequency detector (PFD), Charge pump, Low pass filter, Voltage-controlled oscillator (VCO), Ring oscillator, Frequency divider, Current mode logic, Lock time

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