Analysis, design and optimization of binary to BCD converters
Rangisetti, Sri Rathan
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Decimal information handling applications have developed exponentially as of late subsequently expanding the need to have equipment support for decimal math. Binary to BCD converter is the basic block of decimal digit multipliers. The decimal multiplication involves performing digit-by-digit multiplication in Binary and then converting the resulting Partial Products to decimal. Decimal Partial products are then added as appropriate to form the final decimal product. For this approach to multiplication area, the power consumption of Binary to BCD conversion circuits are essential performance parameters. We can say that with the number of digits multiplied the size of circuit grows, similarly power also increases. The delay of conversion of overall multiplication circuit is same as each Binary to BCD conversion circuit because the conversion of all partial products operates in parallel. Thus optimizing power and area parameters are more important for such multiplication circuit. In this project we analyzed and optimized the existing previous architectures and proposed the novel implementation of the shift-add algorithm using add by a constant technique that makes this design area efficient in compare with existing architectures. The final architecture presented is the implementation of the novel algorithm which we called Range Detection Algorithm in this report. This Range Detection circuit is power efficient in compared with existing architectures. We further progressed to design and implement area-efficient and power-efficient two digits Binary to BCD converter which converts all the possible states 0 to 99.