Standard cell library design and optimization with CDM for deeply scaled FinFET devices

Date

2016-05

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Abstract

In this thesis, we propose the new methodology to achieve the minimum glitch standard cell based design. The Standard cell library has been designed using the logic cells designed in the CDM logic style. The CDM logic style has been analyzed and compared with the conventional CMOS logic style with the FinFET devices in super-threshold operation. Standard cell library with FinFET logic gates in CDM and static CMOS logic style has been developed in various selected technologies (7nm, 10nm, 14nm, 16nm & 20nm) and used to synthesize the ISCAS’85 benchmark designs to evaluate the performance improvement. Synopsys silicon smart and library compiler tool has been used to generate the standard cell libraries using FinFET device models from PTM and design compiler to synthesize the designs with developed standard cell libraries. The simulation results shows that CDM based standard cell library achieve the average power improvement of 17-21% and average PDP improvement of 7-26% for all benchmark designs compared with conventional CMOS standard cell library in 7nm, 10nm, 14nm, and 16nm & 20nm technology node respectively. Hence we demonstrated that our low power standard cell design is comparable to the contemporary custom design optimization techniques used to save power in the design.

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Keywords

Standard cell library, FinFET, Low power design

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