Evolutionary approach for hierarchical scheduling of real-time embedded multicore architectures

Abstract

The aerospace and defense industry is facing an end-of-life production issue with legacy embedded uniprocessor systems. Most, if not all, embedded processor manufacturers have already moved towards system-on-a-chip multicore architectures. Current scheduling arrangements do not consider schedules related to safety and security. The methods are also inefficient because they arbitrarily assign larger than necessary windows of execution. This research creates a hierarchical scheduling framework as a model for real-time multicore systems to integrate the scheduling for safety and security systems. This research provides a more efficient approach that automates the migration of embedded system's real-time software tasks to multicore architectures. A novel genetic algorithm with a unique objective function and encoding scheme was created and compared to classical bin packing algorithms. The simulation results show the genetic algorithm had between 1.8 – 2.5 times less error (between a 56% - 71% difference), outperforming its counterparts in uniformity in utilization. This research provides an efficient, automated method for commercial, private, and defense industries to use a genetic algorithm to create a feasible two-level hierarchical schedule for real-time embedded multicore systems that address safety and security constraints. Hierarchical scheduling frameworks (HSF) are a new scheduling paradigm that integrates multiple system schedules (one-within-another). HSFs present a multi-layered complexity problem that system engineers are struggling to contain. A promising trend in the aerospace and defense industry is to employ Digital Engineering’s Model-Based Systems Engineering (MBSE) to deal with the complexity of HSFs. MBSE permits the abstraction of application-specific details that can radically speed up system design exploration. Thus, this research investigates how the output from an HSF algorithm can be converted into an MBSE modeling language that enables architectural exploration for resource allocation. The Unified Modeling Language (UML) Modeling and Analysis of Real-Time and Embedded Systems (MARTE) Profile is the chosen unified modeling language of MBSE. The modeling language is used with an HSF application for demonstration purposes. The approach in this research seeks to limit tool use by combining an inline verification method (Genetic Algorithm) with a new MBSE workflow.