A switched-current CMOS-only parallel pipelined A/D converter

A pipelined analog-to-digital converter is presented, which employs the switched-current technique to achieve CMOS-only implementation. Four time-interleaved component ADCs are paralleled to increase the throughput to 40Msamples/s, with each operating at the sampling rate of 10MHz. In consideration of linearity and performance, 1.5-bit/stage Digital Error Correction strategy is used and provides 8 effective number of bits for the overall system. For the 0.5pm CMOS implementation, the converter achieves the resolution of 52.1 dB with 500kHz input and its power consumption is 81mW under 3.0V voltage supply. The potential of the ADC is to be integrated in the System-on-Chip for complex applications.