Pessimism of memory built in self test screening with elevated back bias and core voltage

Abstract

V N-well (VNW) biasing is a screening methodology for sub-65 nm silicon semiconductors that provides a means of detecting the effects of Vmin drift often associated with burn-in and time dependent wear-out mechanisms. The following thesis explores the application of utilizing VNW biasing and manipulation of Core operating voltage VDD to model and predict parametric Vmin drift in embedded SRAM arrays of large processors. The goal of this thesis is to quantify the overall effectiveness and coverage of implementing a VNW SRAM screen.