Algorithms for circuit layout compaction of building blocks

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dc.creatorVaradarajan, Ramachandran
dc.date.available2011-02-18T23:45:54Z
dc.date.issued1985-12
dc.degree.departmentComputer Scienceen_US
dc.description.abstractCompaction is the CAD tool used to pack rough sketches or symbolic diagrams to produce error free IC layouts. With the ever increasing complexity of VLSI circuitry, the building block approach becomes very important for custom VLSI design. A graph-theoretic compaction algorithm is developed for the compaction of symbolically specified layouts of building block LSI's. The layout area is reduced by minimizing the pitch in each dimension separately. The algorithm is capable of handling mixed constraints; i.e., the constraints arising from design rule requirements (lower-bound type), and the User defined constraints (equality and upper-bound type).
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/2346/20518en_US
dc.language.isoeng
dc.publisherTexas Tech Universityen_US
dc.rights.availabilityUnrestricted.
dc.subjectComputer architectureen_US
dc.subjectIntegrated circuitsen_US
dc.subjectComputer-aided designen_US
dc.subjectIntegrated circuitsen_US
dc.subjectAlgorithmsen_US
dc.titleAlgorithms for circuit layout compaction of building blocks
dc.typeThesis
thesis.degree.departmentComputer Science
thesis.degree.disciplineComputer Science
thesis.degree.grantorTexas Tech University
thesis.degree.levelMasters
thesis.degree.nameM.S.

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