Improved microprocessor memory testing algorithm

The task of designing, creating and implementing memory testing algorithms for semiconductor devices has become a more complex assignment over the last few years. This challenge has lead to a better understanding of the algorithms and all its surrounding elements.

In this thesis we present improvements made on a memory testing algorithm, the so called "marchl3n" routine. A brief introduction to the SRAM type of memory is presented for a better understanding of the testing algorithm. Strong efforts were made in order to localize and correct the write pending problem. Using a proposed algorithm some modifications were performed to the "marchl3n" algorithm such that is unlikely to present this issue. Moreover, re-design of the "march 13n" algorithm was done to extend its particular use from production only to debug failures. In addition, code optimization was performed to the algorithm, in order to obtain better results from it.