Minimum supply voltage outlier analysis of large scale CMOS devices

The theory and experiment of low voltage testing outlier screening methods will be proposed in this paper. Including an active study of maximum operating frequencies in comparison to their minimum voltage operating conditions. The objective of this paper is to discuss the possibility of using low voltage testing and outlier screening methods to reduce bum in time of large scale Integrated Circuits (IC's). In today's ever growing semiconductor market the need for test time reduction and test cost is ever present. By decreasing test overhead a company has the ability to lower product cost and manufacturing time and at the same time increasing potential profit and revenue.