Switching output stages for direct PCM-PWM amplification with enhanced PSRR and THD performance

This thesis describes the process involved in designing the loop filter that is required when changing a class-D power output stage from a full-bridge configuration to a half-bridge. The loop filter designed is part of an error correction feedback network. This thesis covers the basic theoretical derivations for the device, complete circuit design and simulation and basic device layout considerations. Ideas for future versions are given for reference.