Timing behavior modeling and analysis for Hybrid Logic full adders in bulk CMOS and FinFET

The full adders form a very important part of arithmetic circuits. The full adders are built either in C-CMOS logic style or Hybrid CMOS logic style. C-CMOS logic style is a conventional way to build circuits with a strict methodology of having a pull up and a pull down network. There is also the concept of Logical Effort for effective transistor sizing. Hybrid logic style is a mixture of different logic styles like CPL, PTL, Transmission gates etc. The concept of Logical Effort provides a specific modeling technique for the circuits built in C-CMOS logic style, which enable us to understand the behavior and estimate the delay in single test bench or multistage. In case of hybrid circuits, because of their random structure it becomes impossible to estimate their behavior. Hence this paper presents a ‘Timing Behavior Modeling’ of these hybrid logic full adders which can allow us to estimate their performance in multistage networks. The full adders have been implemented in 32nm Bulk CMOS and 32nm FinFET PTM models.