Study of power consumption for high-performance reconfigurable computing architectures

As reconfigurable computing devices, such as field programmable gate arrays (FPGAs), become a more popular choice for the implementation of custom computing systems, the special characteristics of these devices must be investigated and exploited. Usually a device's performance (i.e., speed) is the main design consideration, however power consumption is of a growing concern as the logic density and speed of integrated circuits increases. Specifically, the characteristic of being reconfigurable gives FPGAs different power dissipation characteristics than traditional ICs.

This thesis explores the problems of power consumption in field programmable gate arrays. An introduction into power consumption and power prediction techniques is presented as well as an overview of the composition of the Xilinx XC4000 Series FPGAs. A probabilistic power simulator, developed under the same research contract as this thesis, is discussed as well as the ongoing attempt to calibrate the power simulator for Xilinx FPGAs.

The design of two different sets of inner product co-processors (multiply-accumulate and multiply-add) for integer and floating-point data is presented. The implementation of these co-processors as well as their performance, sizes, and estimated power consumption values are presented and analyzed in this thesis.