Design, build and test of via test and reliability structures to determine design marginalities in an established semiconductor process

Improvement of yields in wafer fabs is one of the most important goals in modern industry. A good yield results in customer satisfaction, higher revenues and job security. These are not negligible aspects in a successful company. To accomplish them a healthy production with a reliable process flow has to be established in the fab. In the semiconductor industry, common problems as electromigration or stress induced voiding in metal interconnections should be reduced as much as possible or eliminated. Therefore test structures must be built to explore design marginalities for these problems and give further information about the reliability of metal interconnections. This thesis covers different test structures which should detect layout marginalities to avoid any kind of voiding in via in an established process flow and evaluates their reliability. Problems with stress induced voiding, via undercuts caused by a higher etch rate, and resist shrinking due to an oven bake process have resulted in customer returns and need to be investigated. For each of these problems different structures have been designed to find the marginalities. To recreate each issue, process steps thought to be the root cause and already excluded have been reestablished in the flow. The results give information about design marginalities for these issues in the past. The main problem lies in the recreation of the previously observed phenomena, since the wafer fab process is influenced by many seemingly unrelated parameters. Furthermore, reliability test structures have been designed to investigate the robustness of metal interconnections. Additional testing for these structures must be performed to finalize the outcome. In sum, further investigation using the test structures designed in this thesis will enable valuable insights into process robustness.