Sigma-delta modulators with interstage gain scaling

This thesis work describes the efforts made on a new sigma-delta modulator. This unique topology employs an algorithm called interstage gain scaling to depress quantization errors and improve the signal-to-noise ratio (SNR). It consists of two stages: one is a single bit sigma-delta modulator, which is the main stage and the other is a feedback loop stage. At the output of the modulator, the quantization error from the main stage is cancelled while the quantization error from the quantizer in the feedback loop is scaled down by a factor of K. Depending upon the input swing of comparators and operational amplifiers (Opamps) used in the circuits, K can be chosen as 2, 4, 6... For instance, if K is equal to 2, the SNR can be increased by 6 dB or 1 bit compared to the corresponding traditional structure. Successful MATLAB system simulation and PSpice transistor-level simulation in a standard 1.2-um CMOS technology have verified that the proposed sigma-delta modulator is an effective and practicable architecture.