Complimentary based logic design for arithmetic building blocks

High-performance low power arithmetic circuit with reduced area is essential for advanced arithmetic processes. This thesis proposes a modification of arithmetic units using a new design technique which is called Complimentary Based Logic Design (CBLD). CBLD is the design technique which minimizes the number of gates hence improves the area efficiency of the overall circuit. This new design approach can be issued in an arithmetic unit in which multiple blocks perform conditional operations in parallel at one stage or in series with dependency. As multiple module performs in parallel only one module functions and others stays idle. CBLD reduces such idle modules by compressing all modules with a single module. The functionality of CBLD can be verified by implementing it on an optimized module of BCD adder and BCD adder/subtractor module. Comparison of CBLD design with its’ older counterpart shows significant area power and delay efficiency. Second Part of this thesis proposes a novel design of Carry select adder implementing CBLD. Proposed design of conditional BEC-CSLA or modified ripple carry adder is compared with recently published Area power and time efficient Carry select adders.