Characterization of digital phase-locked loops

Phase-locked loops are a relatively new class of circuits used primarily in communication applications. The capture range of a phase-locked loop is a critical parameter because it trades directly with the loop bandwidth. Different architectures for the phase-locked loop (PLL) have been proposed which can broaden the capture range (1-3]. However, in most of the research, very little emphasis was made on studying the exact dependence of the capture range on the different circuit parameters, which define the individual components of a phase-locked loop. The effect of these parameters, for instance, the W/L ratio of the transistors, can be prominent. This thesis is aimed at designing a circuit for a digital phase locked loop, characterizing the components and discussing a method of estimating the capture range. This circuit can act as a starting point in solving the above mentioned problem. The next step would be to observe the dependence of capture range on circuit parameters.