Highly efficient and linear SiGe BiCMOS power amplifiers using envelope-tracking for mobile broadband wireless communications




Journal Title

Journal ISSN

Volume Title



This dissertation presents the design insights towards the realization of a fully monolithic ratio frequency (RF) cascode silicon (Si) BiCMOS power amplifier (PA) using the integrated envelope tracking (ET) technique (i.e., an “ET-PA” system). The dissertation begins with the introduction of ET as an efficiency-linearity enhancement technique by demonstrate its operating principle with the RF/analog/digital system co-simulations in SPICE and analytic analysis. The bandwidth and timing mismatch sensitivities are compared between the ET and the envelope-elimination-and-restoration (EER) techniques. A discrete linear-assisted switching envelope modulator is designed to investigate the overall ET-PA system performances using a monolithic SiGe common-emitter PA for broadband 3G/4G cellular signals with high peak-to-average ratio (PAR). The design trade-off of the switching frequency and the bandwidth of the envelope modulator on the ET-PA will be studied carefully to improve the linearity without degrading the overall efficiency. After the design insights for the circuits and the ET-PA system are well-understood, a fully monolithic SiGe BiCMOS cascode ET-PA will be implemented and presented. The proper circuitry topology and envelope shaping method will be investigated to successfully apply the differential cascode SiGe/BiCMOS PA into the ET-PA system. The integrated CMOS envelope modulator is optimized specific to this cascode PA, where its finite bandwidth and switching frequency are considered for achieving a high efficiency with minimal distortion and low spurious noise. Such optimization of the monolithic envelope modulator design for a fully-integrated ET-PA system is novel and different from almost all the works previously published in the literature. Further improvements of the fully monolithic BiCMOS ET-PA will also be carried out by: (1) the combination of ET and transistor resizing techniques for additional efficiency enhancement at the low output power regions for power saving; (2) the integration of the ET technique with the power-combined SiGe PA with an on-chip transformer for higher linear output power; and (3) the design of the monolithic Bipolar-CMOS-DMOS (BCD) envelope modulator for higher voltage and higher power applications. Based on the literature surveys, all the above monolithic ET-PA designs achieved state-of-the-art world record efficiencies for Si-based RF PAs for broadband high PAR signals without needing any predisotortion technique. More work is underway to increase the maximum output linear power to enable this revolutionary silicon-based ET-PA technology into real products space for various handsets and wireless applications.



Envelope-tracking (ET), Envelope modulator, Power amplifier (PA), SiGe BiCMOS, Sascode PA, Bipolar-CMOS-DMOS (BCD), Efficiency-linearity enhancements, CMOS, Fully monolithic ET-PA system, Broadband cellular communications