Cache resident self testing on passive loopback board

Testing of devices is an important factor in the semiconductor industry. There is a constant effort by major semiconductor companies to bring down test cost and time, without compromising on the test quality. Implementation of built in self test techniques (BIST) are required, especially for complex components like microprocessors. Several challenges are associated with development of BIST techniques and development of such techniques on the ATE is time consuming. This thesis project is an attempt to address the challenges associated with development of a certain BIST, called cache resident self testing (CReST), developed at AMD [5]. In CReST, test vectors are loaded into the cache of the microprocessor, and the processor is used to test itself. In this work, high speed IO links in the processor are tested. The device under test is an AMD processor with a G34 package, having four HyperTransport links.
The work includes debugging an engineering device interface board (DIB), developed to implement the loopback test, avoiding certain tester channels. This passive loopback DIB gives better performance and is expected to be used in production testing soon. A comparison of the loopback and the production DIB is presented. Also the aspects of loopback testing and principles of CReST are discussed, along with an overview of the ATE used for this process