Low power test pattern generation for system on chip devices

Date

2006-05

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Abstract

State of the art developments in the semiconductor manufacturing processes, integrated chip design methodology, availability of thousand plus pin integrated circuit (IC) packaging options and efficient IC test techniques have contributed immensely towards the integration of entire system on a chip.

These System-On-Chip (SOC) devices can include multiple microprocessors, various types of memories such as SRAM, Flash and ROM, Digital Signal Processor(s), dozens of IP blocks and user defined logic.

Various SOC test techniques have been innovated in the last decade to test complex mixed signal systems on a chip in a cost effective manner. The test industry has made great strides in developing new automated test equipment which can test logic, memory and analog components of the chip via external interface to the IC. Advances in the Built-In-Self-Test (BIST) techniques has enabled IC testing using a combination of external automated test equipment and BIST Controller on the chip.

The power consumption of the chip during manufacturing test can be significantly higher than the power consumption of the chip in its target system. This increase in the power consumption can be attributed primarily to on-chip extremely random test pattern generation.

This thesis probes into the various IC test approaches such as external, internal and embedded with specific investigation into the low power test stimulus generation. A new low power pattern generation technique is implemented. Conventional and low power test patterns are applied on an industry standard ISCAS-85 c432 27-channel interrupt controller circuit and average power consumption is measured. The results indicate 60% lower power consumption by the circuit using the new approach for an identical fault coverage of 98% in both cases.

Description

Keywords

Power, TEST, System on a chip (SOC)

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