Low power/low voltage LVDS (low voltage differential signal) receiver design



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Texas Tech University


The focus of this thesis is to investigate the application of low-voltage/low-power design to an LVDS (Low Power Differential Signal) receiver. The power consumption and necessary source voltage levels in current CMOS circuits is dependent on the size of the transistors used and the design topology utilized to realize the circuit.

A CMOS process design solution is desired to reduce the power consumption and source voltage of an LVDS receiver while maintaining full speed operation to improve overall receiver efficiency and lower receiver operating voltage from 3.3V to 1.8V. Testing and optimizing of the design of the low-power/low-voltage LVDS receiver is done through simulation and measurement of various parameters on Pspice. Tradeoffs in low-power/low-voltage circuit design are presented and investigated to determine a solution for real world application.



Low voltage integrated circuits, Complementary, Metal oxide semiconductors, Design and construction, Radio -- Receivers and reception