An on-chip learning neural network

Date

1994-12

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Abstract

In this thesis, an on-chip learning neural network has been designed that uses multiplying digital-to-analog-converters (MDAC) in the synapse. The chip will take advantage of digital processing to learn and store weights, but will retain the parallel asynchronous behavior of analog systems, since part of the neuron functions are done analog. The MDAC unit used in this neural network has an accuracy of 5 bits with separate sign bit and a dynamic voltage range of -2.5V to 2.5V for linear multiplication. It has a much wider dynamic range than most existing designs and also it can multiply in all four quadrants. The same design technique used to design the 5-bit MDAC can be extended to design an 8-bit MDAC, t~ use where more precision is required. In this network, on-chip Hebbian learning is implemented in standard digital logic . Hebbian learning is very attractive for electronic neural networks, since it uses only local information in updating weights.

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Neural networks (Computer science)

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