Adaptation of wafermap bin analysis to erasable programmable logic devices

Date

1991-12

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Abstract

The timely identification of yield loss problems is a primary concern of the semiconductor industry. Numerous methods have been developed to aid in the identification and elimination of process related defects. However, in many cases process defects are not detectable until die are tested electrically and functionally. These tests are not completed until after the wafer manufacturing process steps are complete. The data collected during testing is analyzed to determine yield loss. This test data may be represented graphically as wafermaps. The wafermaps can then be analyzed for failure patterns that can be related to the suspected processes. The analysis of the wafermap failure patterns has been successfully applied to memory devices. The objective of this research is to apply wafermap bin analysis to the programmable logic device family and determine the possibility of applying the memory device database of knowledge to the programmable logic device family. It is shown that wafermap bin analysis can be successfully applied to EPLD's and that solutions to problems causing EPROM yield loss can also be applied to EPLD's.

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Keywords

Integrated circuits -- Wafer-scale integration, Programmable logic devices, Semiconductor wafers

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