Failure Mode Analysis and Design Optimization of 15 kV SiC SGTO Thyristors for Pulsed Power Applications




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SiC SGTO thyristors are an advanced solution for increasing the power density of high voltage pulsed power or power electronics. However, for these devices to supersede the established technologies, their long-term reliability and failure modes must be further understood. This dissertation presents an in-depth analysis of the long-term reliability and failure modes of 1 cm2 15 kV SiC SGTO thyristors during 2 kA 100 μs pulsed operation. The electrical failure modes are determined experimentally with an automated high energy pulsed power system, and the physical failure modes are determined through advanced IR and SEM-FIB microscopy techniques. Next, this dissertation presents the electro-thermal TCAD simulations of the 15 kV SiC SGTO switching 2 kA from a PFN. These simulations were performed in an effort to gain a deeper understanding of the device’s operation and failure modes. Based off the TCAD simulations, a theory of stacking fault formation is put forth as the underling physical mechanism that resulted in the devices’ degradation. The TCAD simulations revealed the buffer layer currently used is insufficiently thick for pulsed power applications. In addition, the design of the 15 kV SiC SGTOs is optimized through TCAD simulations to circumvent the hypothesized failure modes in future devices and to achieve faster switching capability.



Super Gate Turn-Off thyristors (SGTO), Silicon carbide (SiC), failure analysis, thyristor, scanning electron microscope, pulsed power, Technology Computer Aided Design (TCAD)